Khurram1965
Newbie level 4
Dear Friends, I have just start the using CPLD, I need a vhdl code for a 16 bit shift register, who serially out a 16 bit pre-defined hex code like"AC52" on each rising edge of input clock. thanks
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Yes, I know. But the specification is incomplete.I want to transmit serially a 16 bit pre defined code bit by bit on each rising edge of clock
signal sr: std_logic_vector (15 downto 0);
process (clk)
if risisng_edge(clk) then
if load = '1' then
sr <= x"ac52";
else
sr <= sr(14 downto 0) & '0';
end if;
end if;
serial_out <= sr(15);
end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Frameout is Port ( clk : in STD_LOGIC; load : in STD_LOGIC; Serial_out : out std_logic); end Frameout; architecture Behavioral of Frameout is signal sr: std_logic_vector (15 downto 0); begin process (clk,load) begin if (load = '1') then sr <= x"ac52"; else if rising_edge(clk)then sr <= sr(14 downto 0) & '0'; end if; end if; serial_out <= sr(15); end process; end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 signal sr: std_logic_vector (1599 downto 0); signal i,j :integer range 0 to 255; --and assign i=1599 and j=1583. -- and ur code shud be like if (load = '1') then sr <= x"ac52"; else if rising_edge(clk)then sr <= sr(i downto j) & '0'; end if; i=i-16; j=j-16; end if; serial_out <= sr(15); end process; end Behavioral;
I guess, you didn't try to compile. The code is violating various VHDL syntax rules (and doesn't work if the syntax would be tolerated).i hope dis does the work... .
signal sr: std_logic_vector (15 downto 0);
signal cnt: integer range 0 to 1599;
process (clk)
if risisng_edge(clk) then
if reset = '1' OR cnt >= 1599 then
sr <= x"ac52";
cnt = 0;
else
cnt <= cnt + 1;
sr <= sr(14 downto 0) & '0';
end if;
end if;
serial_out <= sr(15);
end process;