Register Banks in RTL

[alchemist1]

Hi All,

Why are register banks used in RTL when it can be a memory. Also wat are difficulties in converting a reg bank to memory.

 

[jpvSoccer]

Hi, memories have benefits, but they also have have physical requirements that flops don't. Flops can go in any row and do not cause routing blockages, while memories typically need to be floorplanned, can require power rings, and block routing.

On the upside, the area per bit of memory is very small when compared to flops.

 

[qieda]

Hi,

register banks
- can have individual reset values
- can have multiple read/write ports.
- can have asynchronous read/writre ports.
(memory normally do not have this)

but

register banks
need more area/power

 

[rca]

a registers bank could be directly implemented in flop, if correctly coded, a dedicated gated clock can be create to match the simpliest flop.
this flop can be include in scan, do not need any bist.

 

[alchemist1]

Hi Guys,

I have an issue. the reg banks are getting spread all over the block and because of that i get congestion as well as timing violations. How best can we implement the reg banks in physical design to minimize congestion ?

Thanks..................