Regarding verification of code

[pankajakc]

Hi,

I am using logic which shown below in my design (synchronous design). its working exactly in simulation (please find the attachment which shows the simulation results) but while implementing the same logic in the post routing simulation, i am able to get the correct results for timing_index2, but for other signals such as timing_index_feedback, timing_index3, timing_index4, timing_index5 will be don't care terms which will come randomly not continuously. so where should i suspect now!

Please suggest me something

always @(negedge valid_buf or negedge ASYNC_RESET)
begin
if(!ASYNC_RESET)
timing_index2<=0;
else
if(timing_valid)
begin
timing_index2<= timing_index_est;
end
else
begin
if(timing_index2==5)
begin
if(k==3)
timing_index2<=3'd0;
end
else if(k==3)
timing_index2<=timing_index2+1;
end
end

always @(posedge valid_buf or negedge ASYNC_RESET)
begin
if(!ASYNC_RESET)
begin
timing_index_feedback <=3'd0;
timing_index3 <=3'd0;
timing_index4 <=3'd0;
timing_index5 <=3'd0;
end
else
begin
timing_index_feedback <=timing_index2;
timing_index3 <=timing_index3;
timing_index4 <=timing_index3;
timing_index5 <=timing_index4;
end
end