Regarding Footed dynamic logic family

[Chinmaye]

Why is the NMOS transistor in footed dynamic logic families always present after the combinational logic is realized? Why cannot it be placed just below the PMOS transistor before the combinational logic is realized?

 

[BradtheRad]

Can you provide a link? Internet search reveals few articles of these methods (described as relatively new).

Diagram grabbed from an extract. The blocks are labelled 'NMOS logic'. Perhaps there remain innate quirks in fabricating N devices versus P devices, such that performance is better with N devices?
Perhaps the logic blocks need consideration in routing circuit pathways, in connecting common ground paths, etc. This may dictate placement, and choice between, N devices versus P devices.

Caption states: left=unfooted dynamic logic. Right=footed dynamic logic.