Regarding conservative and non-conservative systems in Verilog-A/MS

[ams_ei]

Hi,

I am a new with verilog-AMS. I've developed a behavioral model of a lowpass filter.

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Code Verilog - [expand]
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`include “disciplines.vams”
`include “constants.vams”
module lp_filt_beh (sig1, sig2, gnd);
    inout sig1, sig2, gnd;
    electrical sig1, sig2, gnd;
    parameter real res = 1K;
    parameter real cap = 1u;
analog begin
    I(sig1,sig2) <+ V(sig1, sig2) / res;
    I(sig2,gnd) <+ ddt(V(sig2,gnd) * cap);
end
endmodule

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I am not sure whether it is a conservative system or a non-conservative systems.
How can I distinguish between them from the above example?

Explanation would be great helpful.

Thank you.

Warm regards,

 

[pancho_hideboo]

electrical sig1, sig2, gnd;

Conservative System.

 

[ams_ei]

Conservative System.

Could you please explain me why it is a conservative system?

- - - Updated - - -

Is it because the signals are electrical in nature?

 

[pancho_hideboo]

Is it because the signals are electrical in nature?

Yes.
So you can use both flow and potential in description.

If you would like to describe signal-flow modeling, declare sig1, sig2 and gnd as voltage, here you can describe only potential.