regarding always block in verilog

[samuel_raja_77]

always block verilog

1.is it possible to asses memory in an combinational always block like this
always@( a or b or c or d)
begin
addr=a+1;
if( r[addr] == 0)
begin
e=a-3;
end
end
2.in this always block the sensitive list doesnot contain the addr which will be generated in the always block only
3.is it right way of coding

 

[sree205]

always in verilog

Hi,
please take a look at the following link. its for a asynchronous single port RAM. hope this helps.

https://www.asic-world.com/examples....html#Single_Port_RAM_Asynchronous_Read/Write

 

[semiconductorman]

verilog always

If you don't plan do synthesis on this piece of code but only used for verification then it is not a problem but if you want to synthesise this design . My advice is please think hardware. Your code may produce a register array for 'r' variable and then yet may be able to meet timing too!!!!!! but what do i know of the rest of your design or the intent of your code.

 

[Thomson]

always verilog

1.is it possible to asses memory in an combinational always block like this
always@( a or b or c or d)
begin
addr=a+1;
if( r[addr] == 0)
begin
e=a-3;
end
end
2.in this always block the sensitive list doesnot contain the addr which will be generated in the always block only
3.is it right way of coding

Two poential defects if combinational logic is expected:
<1> the if block is not complete -- if you don't like to include the else condition branch, then you'd better put the default assignment at the top of the always block.
you may figure out that if a changes, but the r[addr] doesn't change, then the value is kept unaltered, which means the value of e is latched with a-3 only when the if condition matches.
<2> the varaibles (here means r instead of addr since addr is just a temporary variable in the same block) in the condtion expressions must occur in the sensitivity list, otherwise when the value of expression changes, then output variable is not changed or latched you may say.

One more suggestions: not include the unnessary varaibles in the sensivity list, although this doesn't generate bad behaivors if you adhere to good coding styles.

Suggestions: first read some specific book in regard to the Verilog coding styles and a Verilog Primer before you jump to coding too soon.

Good Luck,

Thomson