Vijay Vinay
Member level 5
Hello all,
I have designed my Clock regeneration circuit in cadence Virtuoso 0.6.1. However, while I was trying to calculate the jitter of the circuitry, there was a bit overshoot and ringing in my circuitry, which I obviously needed to reduce. I need to introduce only capacitors from my bias voltage line to ground, but if I do so, there is no reduction in the ringing or overshoot. I am not sure how to solve this issue. Help is appreciated.
I have designed my Clock regeneration circuit in cadence Virtuoso 0.6.1. However, while I was trying to calculate the jitter of the circuitry, there was a bit overshoot and ringing in my circuitry, which I obviously needed to reduce. I need to introduce only capacitors from my bias voltage line to ground, but if I do so, there is no reduction in the ringing or overshoot. I am not sure how to solve this issue. Help is appreciated.