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Recommend a pulse filter? If pulse longer than 100ms, output, otherwise not

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tony_lth

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Hi, Gurus,
I want a pulse filter to filter false signal.
In my circuit, there is a reset signal.
If I set the reset to low level with more than 100ms duration, my module will reset.
Otherwise, if the duration is less than 100ms, I hope it doesn't. So that the false pulse, such as 10ms duration low level interference signal,
doesn't reset my module.
Could you pls recommend an IC to do so?
many thanks.
Best,
Tony Liu
 

Hi,

AND gate.

There could be numerous other solutions...it could be pure analog, discrete, within an PLD, within a microcontroller.
Refine your specification.

Klaus
 
Hi, KlausST,
Thanks.
PLD and MCU don't fit for, because with limited space and hope with very strong robust, so pure hardware solution is preferred.
Pure analog, discrete, and AND gate all are OK.
I knew RC solution, but I am afraid that precision is not so good. I hope 100ms with about 20% error is acceptable, but I worry that RC exceeds 20% error.
So could you comment ?
Best,
Tony Liu
 

A simple solution would be RC filter with CMOS ST gate, but timing error due to threshold voltage type variation might exceed 20%, although typical variations are much smaller. Monoflop gates have lower guaranteed timing error, capacitor tolerance adds however.

What's the problem if timing error exceeds 20 %? It may be simply an unsuitable spec. If the timing is really critical, go for digital timer.
 
Another option may be to use a 'reset generator' IC, the kind used to delay a reset signal until some time after the power line has been established. They use internal digital timers. Some also have glitch protected external reset inputs you could use.

Brian.
 
Hi,

but I am afraid that precision is not so good. I hope 100ms with about 20% error is acceptable,
There is a good chance that precision stays within 20%..at constant VCC and inhouse temperature range.
But you won't get accuracy within 20%.

MCU don't fit for, because with limited space
I assume a 6pin or 8 pin MCU solution could be smaller than a pure analog solution.


Klaus
 
Hi, All Gurus,
I finally selected ADM6316xxxX, which has a watchdog time from 100ms, from 71ms~153ms.
It is acceptable.
The outside reset signal will be connected to WDI as following.

I still doubt if it can work as my supposed:
1. Normally WDI=+3.3V,
2. when want reset, WDI=0V,
2.1 if WDI=0V last more than watchdog time, then output low (reset signal).
2.2 if WDI=0V less than watchdog time, then output high, no reset happens.

Right?
Best,
tony liu

- - - Updated - - -

Hi,
What I am worried is that outside reset low level can produce two reset signals,
from the down and up transition of outside signal respectively.
Right?
 

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You misunderstand the operation of a watchdog timer. It also resets if WDI stays high for longer than the timeout period.
 
Hi, FvM,
Thanks for comment. I see.

so, Gurus,
I have trouble to find an IC. Although CAT72/71 can function as what I want, which has the least outside input signal duration is 500ms, but I need is less than 300ms strictly.
I browsed tens IC, but most of them control the output reset signal timeout.
What I need is an reset generator IC, which can work when input signal duration is less than 300ms, best between 100ms and 300ms.
Could you recommend an IC for me?
Best,
Tony Liu

- - - Updated - - -

Sorry, it should be "CAT872/871".
PS:
When input signal duration less than about 70ms, I hope no output.
 

The simplest is just to use an RC delay with a Schmitt-trigger input, such as a CD40106, and tweak the value of the resistor to get the desired value, if needed.
LTspice simulation below:
There is no output with a 50ms input pulse and there is with a 70ms pulse.

Capture.PNG
 
According to the +/- 30% delay variation you accepted in post #8, the ST gate solution should be fine.
 
The cheapest solution is probably a PIC10F200, you can set any delay and glitch protection you like within reason, they require no external components and come in 8-pin DIP or 6-pin SMD packaging. You do need to write a program but a simple delay routine isn't rocket science, I would guess the whole program would be less than 10 lines of code.

Brian.
 
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