kranthi_m
Newbie level 4
I want to design a receiver for an I/O which can receive a sequence of bits from the Transmission Line and convert them to digital logic.
One input to the receiver is a constant reference voltage and the other input is the data. The design should achieve less variations in output duty cycle at Typical, Fast and Slow corners.
Can anyone suggest an architecture.
One input to the receiver is a constant reference voltage and the other input is the data. The design should achieve less variations in output duty cycle at Typical, Fast and Slow corners.
Can anyone suggest an architecture.
