dBUGGER
Advanced Member level 4
ieee explore
Hi all,
Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module? This is required to match and assert if the program is working correctly. Please help. Thank you.
Best Regards,
Hi all,
Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module? This is required to match and assert if the program is working correctly. Please help. Thank you.
Best Regards,