param
Member level 2
verilog fread
hi all,
how to assign the input data written in a file to the port, for testbench purpose using verilog hdl?
suppose i have some samples of input data written in .dat file,
and in my testbench i want to input all the values written in that file, how can i do it?
i have tried in the below manner and could not find any data assigned to the input pin while simulating,
data_in = $fopen('' input.dat","r");
please help to solve this.........
hi all,
how to assign the input data written in a file to the port, for testbench purpose using verilog hdl?
suppose i have some samples of input data written in .dat file,
and in my testbench i want to input all the values written in that file, how can i do it?
i have tried in the below manner and could not find any data assigned to the input pin while simulating,
data_in = $fopen('' input.dat","r");
please help to solve this.........