Questions about spikes in 65nm technology and gates

[master_picengineer]

Hi all,
Please who can reply to these 2 questions:

1- For a 65 nm tech (Power supply of 1 V) I obtained spikes of 0.2V. Generally speaking, for a given power supply from which percentage we consider spikes dangerous to our circuits ?
2- For a gate, Spikes in the output can be reduced by increasing the Fall/rise time of the input signals. I don't like this solution coz it require decreasing the frequency. Does anybody know another solutions ?

Thanks in advance for your time.
Regards,

 

[A.Anand Srinivasan]

Spikes

different circuit have different spike control requirement for digital circuits it is mainly related to the noise margin and power consumption....

i dont understand what u mean when u relate fall/rise time with frequency please elaborate your view...

 

[master_picengineer]

Spikes

Hi A.Anand Srinivasan,
Let consider a nand gate and you wanna determine the maximum frequency of it's inputs that support that gate. Suppose that this frequency is F. With such a freq the output signal gives good results but it has spikes. We know that inverter insertion resolves the problem however in introduces additional delay. Another solution that i found is to increase the rise fall time of the inputs which lead for the shrinking of the pulse width already specified. That mean that we must decrease in frequency.
Now that all is clear, can anyone reply to my 2 questions ?

Thanks in adavance.