Questions about process variation...

[gggould]

process variation of poly resistors

Hi all,

I have some questions about the passive device variation.
If those active devices vary from slow corner to fast corner, how would those passive components, such as R, L and C, change their value?
What is the typical r, l and c variation percentage?

Thanks a lot

 

[purefen]

site:www.edaboard.com process variation

Dears:
u should find out the process data sheet which is provided by ur Foundry.
It will give u this information clear and detail. If u don't do this, u will design a chip which is not suit for mass production.

 

[yeewong_su]

process variations vary around typical value

General, you should have the margin of R C + - 20%

 

[nxing]

In Slow process, R and C go up and in Fast process, R and C go down, in general.

 

[sunking]

Most of the foundry can do as +-10% for the passive device.

 

[selvaraja]

Hi,

It depends on type passive device you using example resistors they have poly resistor silicided and nonsilicided , nwell resistor , diffusion resistor so on.Check foundry process document for clear details

 

[gggould]

Thank guys...

I know I should check the foundry menu, but I did not find much detail in that.
Acturally, my question is: "generally speaking", should that variation for all devices "lumped" together (vary in the same direction)???
Because one of my colleague told me the variation for all devices should vary independently.
If that is true, that means I will have LOTS OF corners to run...

Thanks a again...

 

[Teddy]

In general the ss ff corners are designed to move all the devices to the same direction. Something what sometimes does not work even with physics - all the models are just +- 3sigma calculated (mostly 3..) values. Those models are not usualy extracted.They give you lowerleft and upper right corners only. So all the are inbetween is not covered. Ideally (and some foundries recommend it to cover their ...) you should run all the combination what would give you a bit better coverage. It usually comes to about 800 sims to do it.
If you want to be safe you should run MonteCarlo simulation which moves characteristics of each devices independently and not for max +-3sigma increments but also less. Then you would see gaussian distribution which you can relate easier to process.
If you want to see what the change for each device is between ss -tt -ff just dive to a model files.....

 

[okguy]

I think that models are at least 4sigma ... to get at least 3sigma for circuits.
Have an happy time with your monte-carlo sims ...

 

[maxwellequ]

The variations on the parameters of the devices (Transistors, Resistors, Cap...) can be divided in two parts (I'll give the example for resistors):

-Systematic Variations: this is usually referred as Process variations - in this case ALL the resistors in the same lot suffer from the same variation. For example, in one lot you can have ALL the resistors 15 % above the typical value and, in another lot you may have ALL the resistors 10 % below the typ value.
The bottom line is "all the devices in the same lot suffer similar deviations in their parameters"

-Random deviations: These deviations are MUCH SMALLER than the previous ones an occur in equally drawn devices, even if they are very near each other. This depends on the area of the devices. For example you may make a layout in which two equally drawn resistors have (only) a random difference of, say, sigma(DeltaR/R)=0.1 %. This is what causes offset voltages in the circuits.

Your corner simulations must be done using the maximum systematic deviations and, then, if the offset voltages affect your circuit´s performance, you should make monte-carlo simulations.

 

[dini]

Thank guys...

I know I should check the foundry menu, but I did not find much detail in that.
Acturally, my question is: "generally speaking", should that variation for all devices "lumped" together (vary in the same direction)???
Because one of my colleague told me the variation for all devices should vary independently.
If that is true, that means I will have LOTS OF corners to run...

Thanks a again...

Good question.
There is a tool named TRADICA developped by the University of Dresden which answer partially your question. This is in fact dedicated to bipolar transistors using Hicum physics based scalable model.
You enter the PCM data, some design layout aprameters, some known process variations and the tool generate real corner models. You can also optimize your transistor and circuits based on that. As I heard this tool will be installed in cadence environment by soon.
I think the same kind of tools are under development for passive devices.
The final goal is to be able to provide to designers real possibility of circuit optimization.

regards,

 

[chinito]

I have experienced R +- 20%, C +- 35%, L +-30%. Of course, don't forget the parasitics that come along with your layout.