Questions about Phase Detector

[Alles Gute]

hi guys,
We've seen phase detectors PD or phase frequency detector PFD behave like figure (a) shown: in phase locking state, the rising edges of clk_1 and clk_2 are locked. clk_1 and clk_2 have same frequency.
Have you seen "PD" behave like figure (b) shown? clk_1 has several times higher frequency than clk_2. In phase locking state, the rising edges of clk_2 are locked to some rising edges of clk_1.
Alles Gute

 

[fun.zhao]

"PD" only hold the phase error between reference and feedback signal constant (zero or not), if "PD" is a analog multipler, the phase error maybe not "0". and the frequency of reference and feedback maybe not equate

so, your figure is right! because the phase error is constant on "PD".

 

[Alles Gute]

"PD" only hold the phase error between reference and feedback signal constant (zero or not), if "PD" is a analog multipler, the phase error maybe not "0". and the frequency of reference and feedback maybe not equate

so, your figure is right! because the phase error is constant on "PD".

no,

if clk_1 and clk_2 have same frequency(w1=w2), using analog multipler is OK, the multiplication result will have a DC value 0.5AB*cos(phi).
Acos(w1*t+phi)*Bcos(w2*t)=0.5AB*[cos(phi)+cos(2wt+phi)]
Low pass filter the multiplication result we can get what we want.

if clk_1 and clk_2 have different frequency:
Acos(w1*t+phi)*Bcos(w2*t)=0.5AB*[cos((w1-w2)t+phi)+cos((w1+w2)t+phi]
How should you deal with this result?