Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

question regarding RAM access

Status
Not open for further replies.

chadhas

Newbie level 2
Joined
Sep 12, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,293
I have a question regarding how memory is addressed and interfaced to CPU.
Considering I have a 32 bit data bus, and if i have to access (a byte) address on location 0x3, what will i send on my address bus ? Will it be 0x3 or will it be 0x0 and then, pick from the lines 16-23 ? if it is not 0x0 and is 0x3 then what all will be there on rest of the data bus and on what data pins will the value corresponding to 0x3 will come, and how it will be different when i would need to access all 4 bytes in one go ?


Best,
Sachin
 

Is it dependent on CPU ? I had this query in general.
 

well, then it will depends on moon phases and solar storm :)

In general there is also some other control signals for example MEMIO, RD, WR, etc so the answer is

READ DATASHEET
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top