question on post layout simulation

[zjrlgf]

it is a ask_detector schematic, the layout is also drawn(umc18)
then use two tools to extract and post simulate it, assura and calibre

The post simu result of assura is similar to schematic result.
while the calibre result differs a lot to schematic result .

i don't know which one to trust, can anyone give me some help, thanks!

 

[psmon]

Check what you extracted in assura and Calibre.
R & C?

 

[zjrlgf]

yes, just r and c

 

[psmon]

In the transistor model, you can select some options like metal layers.. The parasitics of the metal will be automatically included for simulation. Sometimes the extractor will extract these metals again and add the parasitics to the model, and you have 2 X parasitics.

 

[zjrlgf]

several days ago, i found out that the difference is due to the fact that the finger in schematic is not matched to layout, if matched, the difference disappears.