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[Question]How to shut down a buffer?

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CARFIC

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The topology of the buffer is like a basic inverter. A large capacitor is used to isolate DC in the input signal. Then the signal can be input in the inverter. In addition, a large resistor is employed to connect the input and output of the inverter. When en=0, it works normally; when en=1, it is disabled to save the power. The input signal is always VDD in disable mode. As shown in the attachment.

Now I find in diable mode, the signal after the cap is still VDD/2, so the power consumption of the buffer still has a considerable value. I tried to add more disable MOS in the possible positions, but it didn't work.

So how do I disable it to save the power consumption in disable mode? How do I place my diable transistors?

Thanks a lot.

Added after 53 minutes:

the topology of the buffer
94_1210176332.jpg
 

Hi,
When u connect a resistance between input and output of inverter, u set the operating point of the circuit at Vdd/2. The place where it has high gain and is used for oscillator operation.
U can add a bidirectional PN switch in series with high resistance R and it wont effect the ON operation (provided VTn +VTp < Vdd) and can be switched of by pulling input to either vdd or vgnd.
Hope this helps.
 

It is very nice of you for the words. Actually, I tried your suggestion yesterday. And it didn't work well. Finally, I added a switch in parallel with the cap besides the switch you have mentioned: when in disable mode, the cap is shorted and the inverter doesn't work.
What you think?
 

Add a PMOS in series with your existing PMOS device, also connected to the disable signal. This will allow your disable NMOS to pull down against no load.
 

add an nmos at the bottom with an enable signal
 

To add a disable function to reduce power consumption, u can add a nmos switch in series with the existing nmos or a pmos switch in series with the existing pmos. ALTHOUGH, this would reduce your output swing a little bit.
 

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