question about the ARM7 core ICE pin connecting

[stephen_hu]

hi, any one could help me to solving the ARM7 core ICE pin connecting.
I do not know how to connecting
thanks

 

[littleyard]

Do you get the related inplementation document from ARM? I think once you get the document, read it and then you will not have any problem!

 

[ram]

Hi you need to connect following signals to ICE -
nSRST : in std_logic;
nTRST : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TMS : in std_logic;

please see the ICE pin map in relevlent documents.

 

[stephen_hu]

A7S
(
// Inputs
ABORT, // memory abort or bus error
CFGBIGEND, // big/little endian configuration
CLK, // clock
CLKEN, // clock enable
CPA, // coprocessor absent
CPB, // coprocessor busy
DBGBREAK, // EICE breakpoint/watchpoint indicator
DBGEN, // debug enable
DBGEXT, // EICE external input 0
DBGnTRST, // test reset
DBGRQ, // debug request
DBGTCKEN, // test clock enable
DBGTDI, // EICE data in
DBGTMS, // EICE mode select
nFIQ, // interrupt request
nIRQ, // fast interrupt request
nRESET, // reset
RDATA, // read data bus

// Outputs
ADDR, // address bus
CPnI, // not coprocessor instruction
CPnMREQ, // not memory request
CPnOPC, // not op-code fetch
CPnTRANS, // not memory translate
CPSEQ, // sequential address
CPTBIT, // processor in thumb mode
DBGACK, // debug acknowledge
DBGCOMMRX, // EICE communication channel receive
DBGCOMMTX, // EICE communication channel transmit
DBGnEXEC, // not executed
DBGnTDOEN, // not TDO enable
DBGRNG, // EICE rangeout
DBGTDO, // EICE data out
DBGINSTRVALID, // ETM Instruction valid indicator
LOCK, // locked transaction operation
PROT, // indicates code, data or privilege level
SIZE, // memory access width
TRANS, // next transaction type (i, n, s)
WDATA, // write data bus
WRITE // indicates write access
);

how to use the EICE　ｓｉｇｎａｌｓ，　ｔｈａｎｋｓ