Question about number of cycles in SRAM timing diagrams

[sebmaster]

SRAM Timing

Hello,

I am trying to interface memory with a CPLD and am a little confused about the timing.

I have some 200Mhz CY7C1372D SRAM chips (http://www.cypress.com/?rID=14025)

I am fine with the write cycles, as I understand it:

Cycle 1 - memory latches address
Cycle 2 - data in lines are forced tristate
Cycle 3 - data is acctually stored

(I am only doing single write/reads)

I am confused though about the read cycles. In the datasheet text it describes it as:
Cycle 1 - latch the address
Cycle 2 - data propagates and is present on outputs

But in the timing diagrams it takes three cycles for data to be present at the output.

Further, in an Actel document about SRAM and FPGAs in general (http://www.actel.com/documents/UsingMemory_AN.pdf) the example timing diagram they show for ZBT memory has a read taking three cycles aswell.

Could anyone tell me which I should be designing for? Is the data present on the second or third cycle of a read operation?

 

[sudhirkv]

Re: SRAM Timing

You can go for sampling the data in the 3rd cycle. probably they may use one extra cycle to give the output as a registered data. so u can try sampling in the 3rd cycle.

 

[sebmaster]

Re: SRAM Timing

Thanks sudhirkv, I think that is the way it is meant to be, thats what ill design for.