hqqh
Full Member level 4
Hi,
i'm a little bit confused about the design methodes for ICs.
as i know there are a Top-Down and a Bottom-up design flow.
if i have a top-down design flow like this:
design specification --> behavioral description --> rtl description -->
functional verification and testing --> logic systhesis -->
gate-level netlist --> logical verification and testing-->floor planning-->
physical layout --> layout verification --> implementation
My question:
is it possible to get a transistor-level netlist when the gate-level netlist is created (i want to execute spice simulations)? can somebody provide me a good link about IC design methodes?
thanks in advance,
hqqh
i'm a little bit confused about the design methodes for ICs.
as i know there are a Top-Down and a Bottom-up design flow.
if i have a top-down design flow like this:
design specification --> behavioral description --> rtl description -->
functional verification and testing --> logic systhesis -->
gate-level netlist --> logical verification and testing-->floor planning-->
physical layout --> layout verification --> implementation
My question:
is it possible to get a transistor-level netlist when the gate-level netlist is created (i want to execute spice simulations)? can somebody provide me a good link about IC design methodes?
thanks in advance,
hqqh