question about DRAM cell capacitor from a digital designer

[gerade]

Hi, Guys and Gals,

How much is capacitance of the DRAM cell capacitor for .18 or .11 about?
nx10fF? or?

just want to get a rough idea.

thanks in advance!

Gerade

 

[konqueror]

Re: question about DRAM cell capacitor from a digital design

the DRAM cell capacitor is around 25 or so fF
konqueror

 

[gerade]

Re: question about DRAM cell capacitor from a digital design

thanks for the reply!

and a step further, how much current can the transistor afford to pass, and how much will be the read time and write time for the capacitor for today's DRAM cell? I mean the time the bit line can be drawn down or up a little bit so the sensor can judge there is 1 or 0 (read), and the time bit line write certain value into to the capacitors.

another question
And if you analog designers will deliver a DRAM module to a SOC designer, what kind of spec will you provide, in order to let our digital guys understand. such as timing, power, clock, loading and fanout.

Best regards!

Gerade

 

[nitu]

Re: question about DRAM cell capacitor from a digital design

The information regarding the timing, load etc is passed as done for the standard cell. Also even if one know about DRAM capacitance and its current one cannot judge about its timing because there is some logic part that is used for decoding addresses.
That logic part may seems to be less but that is not true.