mr_byte31
Full Member level 5
System Speed
Hi all
I have a little question about determining the system speed (clock frequency)
Now I have finished my AES system
I wrote all the system in Verilog and then I synthesized it using Synopsys Design Compiler and used TSMC 90nm
now I want to know the max clock frequency that I should use so that the system can run without any violations (setup time, holdup time,..........)
Hi all
I have a little question about determining the system speed (clock frequency)
Now I have finished my AES system
I wrote all the system in Verilog and then I synthesized it using Synopsys Design Compiler and used TSMC 90nm
now I want to know the max clock frequency that I should use so that the system can run without any violations (setup time, holdup time,..........)