question about DDS logic-- reverse engineering

[fpga_asic_designer]

I am looking at a silicon proved design of DDS;
1. Basically use phase accumulater to generate the DTO values, carry_r/carry_f flag,
2. then pass through a module (the one i am cracking my head out but still have no idea how it works) to obtain pointer address for rising and falling.
3. Then the addresses along with address valid would be passed to a rom like logic, choosing appropriate edges from analog for start of rising and start of falling indicater
4. put the start of rising and falling indicaters into an S-R latch, to genertate correct DDS freqency.

All these are simply for open loop.

For #2 module, I understood each line and wrote my own codes out. But I still cannot see the big picture what these repetitive calculations are for. Can any one help me out? I am pasting part of my codes here.

Note: f_o_clk = f_i_clk * SF/(2**16)
Note: dto_width = 16 in this case.

//1st subtraction
wire [dto_width-4:0] sum1 = DTO_div4[dto_width-4:0] - SF_div8[dto_width-4:0];
wire sum1_sign = DTO_div4[dto_width-3] ^ (DTO_div4[dto_width-4:0] >= SF_div8[dto_width-4:0]);
reg [dto_width-4:0] sum1_load;
always @ (posedge irst or posedge iclk)
begin
if (irst) sum1_load <= 'h0;
else if (sum1_sign) sum1_load <= sum1;
else sum1_load <= DTO_div4[dto_width-4:0];
end

//2nd subtraction
wire [dto_width-5:0] sum2 = sum1_load[dto_width-5:0] - SF_div16[dto_width-5:0];
wire sum2_sign = sum1_load[dto_width-4] ^ (sum1_load[dto_width-5:0] >= SF_div16[dto_width-5:0]);
reg [dto_width-5:0] sum2_load;
always @ (posedge irst or posedge iclk)
begin
if (irst) sum2_load <= 'h0;
else if (sum2_sign) sum2_load <= sum2;
else sum2_load <= sum1_load[dto_width-5:0];
end


Thanks a lot!

 

[FvM]

Basic DDS design doesn't involve the said rising and falling parameters, just a frequency register and phase accumulator, optionally phase modulation. It's unclear what you're talking about.

 

[fpga_asic_designer]

Thanks Fvm, I now understood the functionality of the subtraction. Basically it's part of the phase accumulater. It's comparing the accumulated DTO-n*SF values with SF/32, SF2*/32....SF*31/32, to decide which of the 32 edges from analog to choose from....

 

[fpga_asic_designer]

The normal DDS have a low frequency resolution. I.e. if the reference clock is 200MHZ, the frequency resolution is normally also 200MHZ.

This is not very nice, since you cannot have a clock of frequency 160MHZ, only 200MHZ, 100MHZ, 66MHZ (5ns, 10ns, 15ns etc) available.

To achive smaller frequency resolution. Async design is needed using SR latches for squal waves case. Some analog devices could be used to generate reference_clk * #_resolution frequency. A digital design would be needed to devide the incremental_period into #_resolution frequency and compare with the DTO to decide which edge should be used as the rising or falling edge.