question: 2 stage comparator design (low power)

[cmos_ajay]

Dear all,
I need to design a 2 stage comparator that consumes low current.
vdd = 1.4V and idd = 250nA, process is 0.25um cmos

The comparator should work in a "slewing" condition.
Can someone suggest a document or circuit for this ??

Thanks in advance.

 

[leo_o2]

You also need to specify the common input range.

 

[cmos_ajay]

the reference voltage to the comparator will be 0.650V (+/-) 10 %
the other input to the comparator can go from 0V to 0.75V
any other details needed ?

 

[leo_o2]

If no special requirement for speed and offset, common two-stage comparator might be OK. The first stage: differential input; the second stage: common source stage.

 

[cmos_ajay]

Hi Leo,
Is there a design procedure for a low current consumption ( 250nA) two stage comparator ??
I believe the devices may be in weak inversion region for that.
Thanks.