quentions about linearity of LNA

[dot13]

I found that in many papers, the IIP3 was simulated by a two-tone frequencies. But they didn't say how to select the two adjacent frequencies. While in my simulation, if i chose different frequencies, the IIP3 is different according. So what's the criterion?

In fact, i'm desinging a wide-band LNA(50~860MHz) now, the spec gives a IIP3 required. Should I satisfy the request in all the frequency range?

Also, could anyone give me some hints about how to improve the LNA' linearity?

Thanks.

 

[Mazz]

The criterion is linked to the real modulated signal bandwidth on one side and on out of band interferer on the other. If for example your modulated signal has 5MHz bandwidth you can use 1MHz spacing.
I think that you should satisfy it in the whole range, but maybe the spec is not always the same .
Linearity can be improved adding some current to the design. There are a lot of papers dealing with it, it depends on LNA configuration.
I hope it can help.
Mazz

 

[vfone]

As rule of thumb, the spacing between two-tones for receiver IP3 test is 4 times RX channel spacing.
For testing IM3 of a PA part of a transmitter, the distance is one TX channel spacing.

 

[dot13]

Thanks for your reply.
Some papers mentioned that increase Vgs will improve linearity, while when i increase Vgs, the current increase according. So i have to decrease the W/L. then the gm decrease and NF increase.
I want to find a balance point. But the problem is: even the current and NF far beyond the permission, the linearity is still can't satisfy.

 

[springf2000]

i think y'better reference to the concrete application of your LNA, then check the test specification of your concrete system application

 

[Mazz]

i think y'better reference to the concrete application of your LNA, then check the test specification of your concrete system application

Right
some number can help.
Mazz

 

[sunn]

my experience tell me four things would be related to LNA IP3
1. LNA Gain
2. voltage cross transistor
3. bias current of transister
4. senstivity

basically lower gain, high voltage, high bias current and high senstivity could get better IP3 performance. the last one sounds strange but it can allow you to trade off between IP3 and senstivity if you have senstivity margin.

1. and 4. are system level issues, 2., 3. and 4. are related transistor characteristics. so I always choice transistor carefully and do system simulation frequently.

bt the way, Agilent has some good PHEMT transistors could be biased high current and good senstivity still.