Wiljan
Junior Member level 3
Hi
When using Quartus or Prime for a FPGA project and you compile "place and route" will place the different logic as it find "best" somehow, a bit depending on which setting has been set in settings, this will get a fair fMax and does work for many applications.
I do work on some project where I do have like 52 pipeline stages in 1 core and then a lot of the same cores in a FPGA
If I manually assign a LogiLock Region to a core in the ChipPlanner and size it so it will fit tight with the resources it will need and the compile again I do get better fMax.
If I then manually do the same but on each pipeline stage I get even better fMAx, since it places the logic close to each other it the order it needs to connect together. Like if you did a PCB layout you would not place all you logic chips random on the board.
So now for the question:
It get very complex to define those logicLock region manually for all pipelinstages in the ChipPlanner, so I was looking for a way to manually define the first one and then copy this to the rest of the pipelines in the core, and after this copy a whole core.
I did manage to a bit in a tcl script but I would expect there might be a more high level way to do this
Could you please lead me in the right direction
I can also see it possible to create atoms manually but I guess this is to low level.
Thx
When using Quartus or Prime for a FPGA project and you compile "place and route" will place the different logic as it find "best" somehow, a bit depending on which setting has been set in settings, this will get a fair fMax and does work for many applications.
I do work on some project where I do have like 52 pipeline stages in 1 core and then a lot of the same cores in a FPGA
If I manually assign a LogiLock Region to a core in the ChipPlanner and size it so it will fit tight with the resources it will need and the compile again I do get better fMax.
If I then manually do the same but on each pipeline stage I get even better fMAx, since it places the logic close to each other it the order it needs to connect together. Like if you did a PCB layout you would not place all you logic chips random on the board.
So now for the question:
It get very complex to define those logicLock region manually for all pipelinstages in the ChipPlanner, so I was looking for a way to manually define the first one and then copy this to the rest of the pipelines in the core, and after this copy a whole core.
I did manage to a bit in a tcl script but I would expect there might be a more high level way to do this
Could you please lead me in the right direction
I can also see it possible to create atoms manually but I guess this is to low level.
Thx