naseer_39
Newbie level 4
Hi all,
Our requirement is we need to support two 32 MB QDR II SRAMS for Virtex-7 FPGA.
MIG IP core supporting maximum 9MB SRAM. So for one 32 MB Memory Support, we need four 9MB SRAMS and for another 32 MB Memory, other four 9MB SRAMS.So totally we need eight 9MB QDR II SRAMS.
My query is When we try to keep 8 Controllers in MIG IP core it is showing an error in configuration of 5th
Controller.The error is as follows
“ Error: The Configuration Pin PUDC_B is used for all the configurations. This pin falls into the Byte 14–TO. So, please avoid the usage of this FPGA byte.”
Our FPGA Part number is XC7VX485T-1FFG1157
How can we implement 8 controllers in MIG IP Core??
Thanks and Regards,
S.Naseer
Our requirement is we need to support two 32 MB QDR II SRAMS for Virtex-7 FPGA.
MIG IP core supporting maximum 9MB SRAM. So for one 32 MB Memory Support, we need four 9MB SRAMS and for another 32 MB Memory, other four 9MB SRAMS.So totally we need eight 9MB QDR II SRAMS.
My query is When we try to keep 8 Controllers in MIG IP core it is showing an error in configuration of 5th
Controller.The error is as follows
“ Error: The Configuration Pin PUDC_B is used for all the configurations. This pin falls into the Byte 14–TO. So, please avoid the usage of this FPGA byte.”
Our FPGA Part number is XC7VX485T-1FFG1157
How can we implement 8 controllers in MIG IP Core??
Thanks and Regards,
S.Naseer