PSS does not converg

[pancho_hideboo]

My question is :If I assume that circuit is unstable ,
why In pre layout simulation for 1.25Ghz it converge ,
but in post layout si,ulation for f=1.25ghz does not converg?

No.
Netlist of pre layout is stable.
However netlist of post layout is unstable, due to newly added L, M and C.

Observe transient simulation results.

 

[pancho_hideboo]

I think unstable frequency is around 1GHz not 1.25GHz.

 

[Saraadib]

Pancho,
Thank you very much for your reply
can you please explain why you think around 1GHz is unstable?
I have done pre layout simulation and post layout simulation for 1GHz and both converge at 1GHz.
Thanks a lot

 

[pancho_hideboo]

can you please explain why you think around 1GHz is unstable?

Parasitic oscillation around 1GHz could be suppressed by driven 1GHz signal.

 

[Saraadib]

Parasitic oscillation around 1GHz could be suppressed by driven 1GHz signal.

so,for which frequncy is stable then?less that 1GHz ?

 

[pancho_hideboo]

so,for which frequncy is stable then?less that 1GHz ?

No.
Operation is absolutely unstable.
Simply it is suppressed by driven signal.
Unstable frequency is dependent on process corner, temperatre, supply voltage variation.

Do you observe transient result of 1.25GHz drive ?
You should redesign layout to make circuit absolutely stable.

 

[Saraadib]

No.
Operation is absolutely unstable.
Simply it is suppressed by driven signal.
Unstable frequency is dependent on process corner, temperatre, supply voltage variation.

Do you observe transient result of 1.25GHz drive ?
You should redesign layout to make circuit absolutely stable.

I have attched the result of pre layout simulation when clcok=1.25Ghz.
ICan you please take a look ?
I have attached netlist of transient analysis for pre layout simulation for fclcok=1.25Ghz

 

[pancho_hideboo]

I have attched the result of pre layout simulation when clcok=1.25Ghz.
ICan you please take a look ?
I have attached netlist of transient analysis for pre layout simulation for fclcok=1.25Ghz

Show me FFT result with more long time.

 

[Saraadib]

Show me FFT result with more long time.

I have attched FFT result
Thank you very much

 

[pancho_hideboo]

I have attched FFT result

delta_f=0.1GHz(time_length=10nsec)
delta_f<50MHz is required.
So time_length>20nsec

Reshow FFT result with more precise delta_f.

 

[Saraadib]

Attched is dft result of the filter with fclck=1.25Ghz and stop time=40ns for pre layout simulation.
I use this formula for dft .
dft(VT("/net3") 0 40n 512 "Rectangular" 1 "default" )
Can you please take a look

 

[pancho_hideboo]

Why is 1.4GHz missing ?
And why isn’t 1.25GHz included ?

Don’t start with 0nsec for dft().

Waste 0 ~5nsec.

dft(hoge 5n, 45n,

However 5GHz is reasonable.
See https://www.edaboard.com/showthread.php?346629-Moved-N-path-filter-design/page3#50

What node do you observe ?

 

[Saraadib]

Hi Pancho,
I have attched the dft of the output signal for fclck=1.25Ghz for pre layout simulation.
What node do you observe ?output node
I use this expression of dft:
dft(VT("/net3") 5n 45n 512 "Rectangular" 1 "default" )
I have to mention that this filter include clock generator that produce 4 non overlap clock,I have injected 5GHz clock at the input and clock produce for non overlap clock at 1.25Ghz .therefore clock frequency is 1.25Ghz

 

[pancho_hideboo]

Why does it show spectrum at 1.4GHz in first dft() result ?

 

[dick_freebird]

OK, I have only a spectator's idea of what PSS is but
I do not see discussed here, the key question of whether
the transient analysis says the circuit -is- periodic at
1.2500000000000000000GHz or -is not-. That it is at
1GHz might be both good (it -can- be periodic) and/or
bad (maybe not periodic at all frequencies - like maybe
there's some legacy source in the hierarchy still set to
1GHz making numerical trouble).

Have you tried running a multi-cycle transient and
"rasterize" it (like an eye diagram) just to see whether
you have a stable waveform up and down the signal
chain at least?

 

[pancho_hideboo]

(maybe not periodic at all frequencies - like maybe there's some legacy source
in the hierarchy still set to 1GHz making numerical trouble).

I don't think so, since pre layout simulation can be converged with fundamental freq=1.25GHz.

There are three options for parasitic extraction of layout.

(1) Only C
(2) C and R
(3) C, R and L

(3) can not be converged.

Try (1) and (2).

 

[Saraadib]

Thank you for your reply Pancho.
I am confused with something, you said circuit might be unstable and try to change the layout. So, you ask me to do a transient analysis from 0 t0 45n.I did transient analysis from 0 to 45n for pre-layout simulation for fclok =1.25Ghz. I should mention that pre-layout simulation for fclcok=1.25GHz converge, however, it does not converge for postlayout simulation.
So, my question is: is this circuit unstable?I sent you dft result of the pre-layout simulation, and I did dft from 5n to 45n.
so,you said Try (1) and (2), you mean I should do parasitic extraction for R and C only to be able to converge for 1.25Ghz for pre-layout simulation?
and you ask :Why does it show spectrum at 1.4GHz in first dft() result ? becuse it depend on number of sample.I mean if I use this formula for dft:
dft(VT("/net3") 5n 45n 256 "Rectangular" 1 "default" ) ,I will see 1.4Ghz.I have attched the dft result for 256 sample named 256.
But If I use this formula:dft(VT("/net3") 5n 45n 512 "Rectangular" 1 "default" .I see somthing else.I have attched and name it as 512.

 

[pancho_hideboo]

I mean if I use this formula for dft:dft(VT("/net3") 5n 45n 256 "Rectangular" 1 "default" ) ,
I will see 1.4Ghz.
...........
But If I use this formula:dft(VT("/net3") 5n 45n 512 "Rectangular" 1 "default" .
I see somthing else.

1.4GHz is an alias of 5GHz.

delta_f=1/(45n-5n)=25MHz

For N=256, fs=N*delta_f=6.4GHz, fnyquist=fs/2=3.2GHz < 5GHz, 5GHz-fs=-1.4GHz

For N=512, fs=N*delta_f=12.8GHz, fnyquist=fs/2=6.4GHz > 5GHz, 5GHz-fs=-7.8GHz

So your first dft() setting is not appropriate.

You have to set N larger than N*delta_f/2 >> 3*5GHz.
For example, set N=2048.

I am confused with something,
you said circuit might be unstable and try to change the layout.

Right.

I should mention that pre-layout simulation for fclcok=1.25GHz converge,
however, it does not converge for postlayout simulation.

Simply there is problem in your layout.

So, my question is: is this circuit unstable?

Physical design is unstable.

I sent you dft result of the pre-layout simulation,
and I did dft from 5n to 45n.

No.
Show me dft() results of post-layout Transient simulation of (1), (2) and (3).

so,you said Try (1) and (2),
you mean I should do parasitic extraction for R and C only to be able to converge for 1.25Ghz
for pre-layout simulation?

No.
You have to do post-layout Shooting-Newton-PSS simulation of (1) and (2).
Then you might be able to get any clue for cause of unstability in your layout.

Still you can not understand simulation at all.

Netlist of pre layout is equivalent to netlist of post layout with setting all extracted parasitic C, R and L zero.

 

[Saraadib]

Hi Pancho,
Thank you very much for your reply,
I have a qustion about the measurement of this kind of circuit .I use PSS+PAC to simulate this circuit
how should I measure it?Should I use S -parameter to measure this circuit?

 

[pancho_hideboo]

I use PSS+PAC to simulate this circuit
how should I measure it?
Should I use S -parameter to measure this circuit?

I can not understand what you want to mean at all.
What do you want to mean by “it” ?