[SOLVED] PSRR Inverter(logic) agaist input

[Jinkyu]

Hello~

do you happend to know about PSRR for logic inverter input stage?
Power supply noise reflect to input of inverter with -1.4dB.
Plz, someone explain why. someone says that because of source follow, but I don't think so.
Thanks

 

[varunkant2k]

Cgs of the PMOS device is coupled to you supply. Its always a problem and to rectify that you need to cascode the device or use decoupling cap between gate to ground.
But PSRR is not a problem with inverter as it is non-linear device. PSRR is bad for linear device. If you still want to remove in inverters and if used in sensitive blocks as VCO/delay line, use hysteresis, or schmitt triger inverter.

 

[saro_k_82]

In your setup, the PMOS is on so output is shorted to the supply, any variation in supply would be faithfully observed at the output.
Inverters dont have to be immune to supply noise as such. As long as the rise/fall times of the inputs are sharp enough, noise on inverter supply does not degrade any parameter of the signal that it passes.

 

[Jinkyu]

In your setup, the PMOS is on so output is shorted to the supply, any variation in supply would be faithfully observed at the output.
Inverters dont have to be immune to supply noise as such. As long as the rise/fall times of the inputs are sharp enough, noise on inverter supply does not degrade any parameter of the signal that it passes.

Thanks for response.

It's not psrr for VDD vs inverter's output. It's for VDD vs VIN.

---------- Post added at 03:52 ---------- Previous post was at 03:49 ----------


Acutually, I use startup(logic) to sense BGR voltage. It causes PSRR degradation.
So I add LPF to reject power supply noise.

 

[varunkant2k]

I am eager to know if you get any improvement.

 

[Jinkyu]

This is with and without LPF.

 

[varunkant2k]

Yes this is good, but problem is at low frequency noise at supply. Any way good.

 

[saro_k_82]

Startup circuit should be sleeping during normal operation. PSRR degradation due to startup circuit circuit implies bad design and trying to solve it by brute filtering would be both costly as well as reduce only some parts of the problem. Check the PSRR without startup circuit (Could start the bandgap with initial conditions) to confirm that it is due to the startup circuit. Then design one correctly and turn it off fully after reaching close to the operating point.

 

[Jinkyu]

Thanks. sara_k_82
Startup circuit doesn’t work for normal operation. Startup’s input is connect to BGR’s output.
So, PSRR is depredated because of parasitic Cgs in startup circuit. Noise is coupled with Cgs.

 

[saro_k_82]

The CGS of transistors that are off would be in fF or aF range which would be too low to cause any degradation in the frequency range that you have problems with.