Programmable integer divider in Phase locked loop (PLL )

[Dines]

We are using programmable integer divider of this PN : UXN40M7K in our Phase locked loop (PLL ) system. We are facing 2 problem for practical implementation. In the programmable integer divider as electrical characteristics suggest that maximum power to give Pin (dBm) at 10 for division. .

We have given maximum power for input but division isn't happened. It is working only if we exceed the range, for example Pin (dBm) to operate at 10-15 dBm (more than that of suggested max power). An another problem we have faced it, divide modulus control logic for division. they suggested the control logic for 4 division but we tried with the same logic instead to giving 2 division at output.

Can anyone please share your view on this ?

 

[FvM]

There might be a problem with input signal connection, e.g. missing AC coupling. Can you show how you apply the input signal, what's the frequency range you are testing?

 

[BigBoss]

Dividers work in limits of applied input power. Beyond these levels ( both, lower and higher ) the divider either oscillates or saturates. Therefore you should request "safe operating input level" specification from the manufacturer.

 

[biff44]

did you read the DATA SHEET?
specifically, they want you to feed the inputs DIFFERENTIALLY, thru DC Blocking capacitors, and use the internally generated Vcm to achieve the proper DC bias operating point.

are you doing all three of those things?

the outputs need to be ac coupled too with a very specific bias network.

Read up on figures 17 and 18 in the data sheet an come back here to discuss further.

If you did not use the corect biasing methods required,you probably blew out the chip. so solder on a new one and start again.

 

[Dines]

There might be a problem with input signal connection, e.g. missing AC coupling. Can you show how you apply the input signal, what's the frequency range you are testing?

We are operating from 10 to 15 GHz and Input is differential signalling at 4 and 5 as per in the pin configuration.

 

[dick_freebird]

Are you sure that you are reading, interpreting the datasheet correctly? When I see you mention a "maximum to get division" that makes no sense but from doing more than a few electrical tables I might guess that you're looking at a spec for the maximum that the "minimum power to get division" can be. Get it? They guarantee that if you're above this max, Pmin(in) number it'll work. And that seems to be the story. So?