Problems with DFFs without RESET in simulation

[klop]

I have registers which don't use reset(or set) input in my design. When I start to simulate such a design I have a lot of problems (especially after P&R) because of 'X'. Is there any way to resolve such a problem.
Many thanx in advance.

 

[nand_gates]

Just after resetting other FFs with reset force some random values to
FF without reset and release.

 

[amaccormack]

If your design has scan, you may be able to scan a good reset vector into the design. Obviously, if you can change the design to have a reset then better.

 

[Sparc]

U r getting 'X' in ur simulation only in the begining few ns time in Post P&R. Is it?? or u r getting 'X'es in between simulation. If they are coming even in mid simulation, chek if u r not violating Set-up hold.

 

[leeenghan]

Hi klop,

I think it is common to "zero-out" the setup and hold check for synchronizer FF in the SDF file. For the rest of the FF if the simulation can be recover from "X" after initialization it is fine, if not might need to study them one by one to ensure it is not a problem in real chip.

Regards,
Eng Han

 

[jjww110]

you can use force then release force

 

[ms2004]

Hey there,

It is very common to have "x" during full timing SDF simulation. If your simulation is with postlayout netlist, and +notimingchecks and +delay_mode_zero You need to worried really,, but very little.

Most of the PnR tools will change/optimize the logic in such as way that it will work in actual silicon, but can not simulated because of the uninitialized registers. So check your PnR tool, and look for any bug history about optmization.

-Milind Sonawane

 

[shankarmit]

hi

i thick u will get x only in the first few ns ,same problem occurs when i designed pipelined adders. because if u dont have reset in your dflipflop then the initial value assumed may be 0 or 1 or even undefined, so when your dflipflop gets some value two values are forced at time so u get x. but a perfect design must have flipflop with synchronous or asynchronous reset.flipflop without reset must be avoided.since your design is implementing real hardware where reset are must for any operation

 

[stephens_forest]

a good design practice is to use DFF with reset input,

no reset input, DFT will be impossible.

best regards

I have registers which don't use reset(or set) input in my design. When I start to simulate such a design I have a lot of problems (especially after P&R) because of 'X'. Is there any way to resolve such a problem.
Many thanx in advance.

 

[soccer]

It is very common for this situation during post-layout simulation.
Check your layout to look for log file about optmization.

 

[Thomson]

First the causes about the X shall be found.

you can simulate your design with two-state simulation options and according to the advices listed above.

If these ways have been tried, then the major reason is that some timing violations are encountered. Please go back to check and modify.

Another portion may generation X even the above methods are tried, may be that clock-domain issues are not correctly handled or the 2DFFs synchronizer timing setting is not correctly set during the dynamic simulation.