Sunayana Chakradhar
Member level 5
Hello All,
I am trying to synthesize AES encryption algorithm in vivado which was uploaded on open cores as shown in the link below
https://opencores.org/project,aes-128_pipelined_encryption
When I synthesize it, i get the following errors
Can someone tell me how to rectify these errors?
I am trying to synthesize AES encryption algorithm in vivado which was uploaded on open cores as shown in the link below
https://opencores.org/project,aes-128_pipelined_encryption
When I synthesize it, i get the following errors
[Place 30-415] IO Placement failed due to overutilization. This design contains 258 I/O ports
while the target device: 7z020 package: clg400, contains only 255 available user I/O. The target device has 255 usable I/O pins of which 0 are already occupied by user-locked I/Os.
To rectify this issue:
1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.
2. Check the top-level ports of the design to ensure the correct number of ports are specified.
3. Consider design changes to reduce the number of I/Os necessary.
[Place 30-68] Instance clk_IBUF_BUFG_inst (BUFG) is not placed
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Can someone tell me how to rectify these errors?