sebblonline
Newbie level 5
Hi,
I'm using the UDP/IP Core from opencores.org.
My problem is to realize a best effort transmission from the FPGA to the PC. In the following code snippet I have two processes to transmit constant data. The send process is sending as soon as the destination is ready (ctrl_tx_phase_on=1). With the second process I control the start_enable signal. There I have a built-in delay (with the variable k) between two datagrams. When I leave out the counter k (for a true best effort transfer!) the datagrams are not sent correct any more. In wireshark I can notice, that the length of the data is not correct (length of data < number in length-field).
Can someone give me a hint, where my mistake actually is or how that kind of functionality is made right?
thanks a lot in advance,
sebastian
I'm using the UDP/IP Core from opencores.org.
My problem is to realize a best effort transmission from the FPGA to the PC. In the following code snippet I have two processes to transmit constant data. The send process is sending as soon as the destination is ready (ctrl_tx_phase_on=1). With the second process I control the start_enable signal. There I have a built-in delay (with the variable k) between two datagrams. When I leave out the counter k (for a true best effort transfer!) the datagrams are not sent correct any more. In wireshark I can notice, that the length of the data is not correct (length of data < number in length-field).
Code:
send_proc : process (ctrl_clk)
begin
if rising_edge(ctrl_clk) then
if ctrl_reset = '0' then -- global reset
datagram_length <= MAX_DGRAM_LENGTH;
if cnt < datagram_length then
if ctrl_tx_phase_on = '1' then
dgram_sent <= '0';
ctrl_tx_data_out <= "01010101";
cnt <= cnt + 1;
else
cnt <= 0;
end if;
else
dgram_sent <= '1';
cnt <= 0;
end if;
end if; -- reset
end if; --clk
end process send_proc;
enable_proc : process(ctrl_clk)--frame_buf_valid, cnt)
variable i : integer := 0;
variable k : integer := 0;
begin
if rising_edge(ctrl_clk) then
if dgram_sent = '1' and i = 0 then
if k < 100000 then
k := k + 1;
else
i := i + 1;
ctrl_tx_start_enable <= '1';
end if;
else
k := 0;
i := 0;
ctrl_tx_start_enable <= '0';
end if;
end if;
end process enable_proc;
Can someone give me a hint, where my mistake actually is or how that kind of functionality is made right?
thanks a lot in advance,
sebastian