Problem with single slope ADC circuit

[Sheritronics]

I am using the given below circuit the problem is that counter doesn't counting, wat to do i am using multisim 11 to simulate

 

[D.A.(Tony)Stewart]

EN1 = high always
MR goes low when U2(+) exceeds 2V switching on Q1 to dump C Voltage and then (+) goes low , then counting is Reset.

I think MR needs to be inverted.or counter disabled with EN1=0 until counter is read, then do reset Q1 and MR=1

not sure where you got design, I did not verify completely, but I recall Labs using RCA app notes that had errors in a staircase generator I had to fix. Use logic to debug.

 

[Sheritronics]

i am using the same logic but still not getting why this circuit is not working

 

[D.A.(Tony)Stewart]

I mean your logic and debug it.. If + is higher than - on U2 what happens?

 

[Sheritronics]

my logic is that when the output off U2 is - then not gate will resets the counter simply

 

[D.A.(Tony)Stewart]

I am using the given below circuit the problem is that counter doesn't counting, wat to do i am using multisim 11 to simulate

Sorry, but this design is incomplete. ADC needs 2 signals clock and strobe data. After data is read in, the strobe can go low to reset counters and start another conversion. A state latch is needed to disable counter and tell MPU, data is ready.

Another method is to handshake Start conversion from MCU and then wait for Data Ready. which disables counter. (EN)

In this design when U1out>2V , counter should be stopped, not reset.

This design wont work
it resets the counter, rather than drop EN. you can't control when this happens.

So add a signal to start conversion and , then reset Q1 , counter and enable counting for next conversion. It will then latch data by stopping counter when done.

 

[Sheritronics]

Can you do me favor if u could design it again as you said so that will be easy to understand.. but initially it helped little bit to understand some how this adc can be implemented tnx!

 

[D.A.(Tony)Stewart]

Try again. Draw the signals and note what should happen, then design it with extra FF and control signal.

....So add a signal to start conversion and , then reset Q1 , counter and enable counting for next conversion using a monopulse.
It will then latch data by stopping counter when done with EN. You have two EN inputs.


Also choose f clock for desired max rate of VEE and RC ramp to +2V

 

[Sheritronics]

Can you please design me a working circuit i really need it :'(