Cesar0182
Member level 5
Greetings ... tell you that a couple of days ago I have been translating a verilog project to vhdl in Vivado 2017.3, I have managed to synthesize and implement this new vhdl project ... but I can not conclude correctly with the simulation in Modelsim 10.5, due to the next module.
The original code in verilog is as follows.
The problem apparently is the initialization and the assignment of states to output signals of the module, but I'm not sure about that.
Can someone please help me with this problem? In addition I leave attached the report of Modelsim of a correct simulation, and the one that I am obtaining when adding the vhdl module.
- - - Updated - - -
tell them that I have just added all the vhdl modules to the project, and I am having the following warnings in Modelsim and they all indicate the same warning.
But this time the report ends in a failed result. I leave the full report attached.
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity g1_wbus_stack_sm_vhdl is
PORT (
i_clk : IN std_logic;
i_rst : IN std_logic;
i_fifos_almost_full: IN std_logic;
i_rxff_empty : IN std_logic;
i_payload_done : IN std_logic;
o_wbus_wen : OUT std_logic;
o_hdr_en : OUT std_logic;
o_rxff_ren : OUT std_logic;
o_dw_select : OUT std_logic_vector(2 DOWNTO 0));
end g1_wbus_stack_sm_vhdl;
architecture Behavioral of g1_wbus_stack_sm_vhdl is
type state_type is (Idle,Ren_Hdr,Hdr,Wbus_Wen,Wait4ffs,Ren);
SIGNAL g1_wbus_stack_sm_sm : state_type; -- Current State ( Register )
SIGNAL g1_wbus_stack_sm_next : state_type; -- Next State ( Combinatorial Bus )
SIGNAL count_clr_l : std_logic;
SIGNAL scount : std_logic_vector(2 DOWNTO 0);
SIGNAL ready_for_next : std_logic;
begin
------
\sc_\ : entity work.slave_cntr generic map(3)
PORT MAP (
c => i_clk,
ar => i_rst,
ce => count_clr_l,
q => scount);
STATE_REG : process (i_clk,i_rst)
begin
if rising_edge(i_clk) then
if (i_rst = '1') then
g1_wbus_stack_sm_sm <= Idle;
else
g1_wbus_stack_sm_sm <= g1_wbus_stack_sm_next;
end if;
end if;
end process;
ready_for_next <= NOT i_rxff_empty AND NOT i_fifos_almost_full;
NEXT_STATE_COMB_LOGIC: process (g1_wbus_stack_sm_sm)
begin
case (g1_wbus_stack_sm_sm) is
when Idle =>
if ready_for_next = '1' then
g1_wbus_stack_sm_next <= Ren_Hdr;
else
g1_wbus_stack_sm_next <= Idle;
end if;
when Ren_Hdr =>
g1_wbus_stack_sm_next <= Hdr;
when Hdr =>
if scount = "011" then
g1_wbus_stack_sm_next <= Wbus_Wen;
else
g1_wbus_stack_sm_next <= Hdr;
end if;
when Wbus_Wen =>
if i_payload_done = '1' then
g1_wbus_stack_sm_next <= Idle;
elsif scount = "111" and ready_for_next = '1' then
g1_wbus_stack_sm_next <= Ren;
elsif scount = "111" then
g1_wbus_stack_sm_next <= Wait4ffs;
else
g1_wbus_stack_sm_next <= Wbus_Wen;
end if;
when Wait4ffs =>
if ready_for_next = '1' then
g1_wbus_stack_sm_next <= Ren;
else
g1_wbus_stack_sm_next <= Wait4ffs;
end if;
when Ren =>
g1_wbus_stack_sm_next <= Wbus_Wen;
when others =>
g1_wbus_stack_sm_next <= Idle;
end case;
end process ;
o_dw_select <= scount;
end Behavioral;The original code in verilog is as follows.
Code:
`timescale 100ps/100ps
module g1_wbus_stack_sm (
input i_clk, //
input i_rst, //
input i_fifos_almost_full, // Client fifos not ready
input i_rxff_empty, // stack fifo empty
input i_payload_done, // LENGTH DWs have been written
output o_wbus_wen, // WBus Write enable
output o_hdr_en, // Read first 256 bits incl. TLP header
output o_rxff_ren, // Read stack fifo
output [2:0] o_dw_select // Choose the outgoing Double Word
);
reg [7:0] g1_wbus_stack_sm_sm; // Current State ( Register )
reg [7:0] g1_wbus_stack_sm_next; // Next State ( Combinatorial Bus )
wire count_clr_l;
wire [2:0] scount;
slave_cntr #(3) sc_( .c( i_clk ), .ar( i_rst ), .ce( count_clr_l ), .q( scount ));
parameter Idle = 8'b0000_0000; //
parameter Ren_Hdr = 8'b0011_0001; //
parameter Hdr = 8'b0101_0010; //
parameter Wbus_Wen = 8'b1001_0011; //
parameter Wait4ffs = 8'b0000_0100; //
parameter Ren = 8'b0010_0101; //
assign o_wbus_wen = g1_wbus_stack_sm_sm[7];
assign o_hdr_en = g1_wbus_stack_sm_sm[6];
assign o_rxff_ren = g1_wbus_stack_sm_sm[5];
assign count_clr_l = g1_wbus_stack_sm_sm[4];
always @(posedge i_clk or posedge i_rst)
begin
if( i_rst )
g1_wbus_stack_sm_sm <= Idle;
else
g1_wbus_stack_sm_sm <= g1_wbus_stack_sm_next;
end
wire ready_for_next = ~i_rxff_empty & ~i_fifos_almost_full;
always @(*)
case ( g1_wbus_stack_sm_sm )
Idle:
if ( ready_for_next )
g1_wbus_stack_sm_next = Ren_Hdr;
else
g1_wbus_stack_sm_next = Idle;
Ren_Hdr:
g1_wbus_stack_sm_next = Hdr;
Hdr:
if ( scount == 3'h3 )
g1_wbus_stack_sm_next = Wbus_Wen;
else
g1_wbus_stack_sm_next = Hdr;
Wbus_Wen:
if ( i_payload_done )
g1_wbus_stack_sm_next = Idle;
else if ( (scount == 3'h7) & ready_for_next )
g1_wbus_stack_sm_next = Ren;
else if (scount == 3'h7)
g1_wbus_stack_sm_next = Wait4ffs;
else
g1_wbus_stack_sm_next = Wbus_Wen;
Wait4ffs:
if ( ready_for_next )
g1_wbus_stack_sm_next = Ren;
else
g1_wbus_stack_sm_next = Wait4ffs;
Ren:
g1_wbus_stack_sm_next = Wbus_Wen;
default:
g1_wbus_stack_sm_next = Idle;
endcase
assign o_dw_select = scount;
endmoduleThe problem apparently is the initialization and the assignment of states to output signals of the module, but I'm not sure about that.
Can someone please help me with this problem? In addition I leave attached the report of Modelsim of a correct simulation, and the one that I am obtaining when adding the vhdl module.
- - - Updated - - -
tell them that I have just added all the vhdl modules to the project, and I am having the following warnings in Modelsim and they all indicate the same warning.
Code:
# ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_wbus_wen has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_hdr_en has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_rxff_ren has no driver.
...
...
...But this time the report ends in a failed result. I leave the full report attached.
