Problem with 2-stage flash ADC layout

[gunturikishore]

Hi,

My company(Its a small company actually) got a two stage 8-Flash ADC fabricated and it got worst performance. They asked me to debug, when I see the circuit simulation its performance is ok. But when I simulated the post-layout circuit it has problem in the nets input buffers circuits. Its is showing unusual behaviour at one point in a linear ramp input and at other points the performance is ok ( but not exactly linear).

I tried to dig further and I came across a point which I am not sure of how much effect it has on the overall perofrmance.

The input analog signal is buffered in a unity gain opamp and the output of it is going to a Sample and Hold circuit. but inbetween these two circuits the wire is crossing about 8 non-overlapping clock wires laid as a bus, perpendiculalry in the layout. How much the above mentioned layout can have on the overall performance.

I am just practicing the layouts after working for a year on only circuits.

Thank you in advance for the suggestions.

 

[MikeR]

ADC Layout problem

The output of buffered opamp is differential ?

 

[gunturikishore]

Re: ADC Layout problem

No it is single ended. From Sample and Hold circuit everything is differetial.

 

[okguy]

Re: ADC Layout problem

If it is 2stage flash ADC, it should be fast ADC, isn't it ?
So, single ended is a non-sense, because the digital will make a lot of noise that will come on to signal.
If you keep on working with single ended, split as much as you can analog and digital, especially within the ADC. Split the power supplies, use star-routing. Finally fill any blank layout area with a maximum of decoupling caps :!:

 

[gunturikishore]

Re: ADC Layout problem

Hi Actually the signal is coming single ended into the chip, which is converted to differetial at Sample and Hold stage. All the conversion stages are fully differetial.

My ADC is is targeted for 12MSPS application and we target atelast 16 MHz reliable operation at design level. Circuit is working ok and after layout there is problem.

What I can observe is after somepoint the SHA is going into oscillations. I am not sure how it is happening. I chcked with all kinds of loading the amplifier. There is no way that it can go into oscillations from design perspective. But the layout has probelm definitely. I am trying to figure out whether it is oscillation or some shoot up which may die after sometime.

 

[renwl]

ADC Layout problem

maybe the margin is not enough.
you can include the parasitic cap into the pre-simulation.

 

[najmuus]

Re: ADC Layout problem

No it is single ended. From Sample and Hold circuit everything is differetial.

 

[yellff]

Re: ADC Layout problem

I think the LSB comparator's layout ,and the reference is very crtical.