problem in 'while' loop in VHDL

[scanman]

Yes, the RDY output = 1 when data output is ready.
The RST is used to start the state machine running otherwise
it stays in "Idle" state. When all inputs are stable then RST is set
to 1 and then 0 after 1 clk or so. Then wait for RDY = 1.

scanman

 

[rourabpaul]

im trying to remove this rst input for my purpose,
is it possible?

 

[scanman]

I can not think of another way to start the state machine cycle.
How do you want to start the divider? Do you want it running continously?

 

[rourabpaul]

actually i have a continuous digital data(1 million per second almost),which would continuously modulated by modulus operator,so i want avoid complicity,
so i want to avoid this 'rst',could we?

 

[scanman]

Yes it is possible to have divider run non-stop.
This would require code modifications to suit your design.
You must synchronize your data inputs and outputs correctly.
This will require some timing analysis.

 

[FvM]

Yes it is possible to have divider run non-stop.

It's a serial divider that needs a number of clock cycles to calculate the result, about 8 + number of bits in this case. It can only calculate one new result each 20 cycles, in contrast to a pipelined parallel divider that gives a new result each clock cycle. In so far, it doesn't help much to omit the rst (start) signal and make the divider restart automatically from the idle state.

 

[rourabpaul]

I have removed the rst,and it now giving desired result, thank you to all of you,
and a special thanks to scanman,
one another thing i want to know,could we use a separate process in a main process?

Rourab Paul

 

[scanman]

Rourab,

Your welcome! Glad it worked out.
Normally I place all my processes within the architecture framework:

architecture Behavioral of my_main_code is

declare all components here

declare constants and signals here

begin -- start of main process

new_process_1 : process (sensitivity list) -- new process 1

begin

end process : new_process_1;

new_process_2 : process (sensitivity list) -- new process 2

begin

end process : new_process_2;

-- main process code here

end process : my_main_code;

Regards,
scanman

 

[rourabpaul]

okkay,
suppose i'v a process which is clock sensitive ,and i want to use another program (say your divider program) which is also sense the same clock input of the main program by port mapping ,could we?

main process(clk)
begin
port map modulus (fiormal port=>actual port, --modulus program has a
--------------------------, --process which is also clk sensitive
--------------------------,
clk=>clk);
end process;

 

[scanman]

You declare the divider as a component of your main entity which has CLK as input.
Then you make CLK as input to divider as well. Here is example:

https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/

scanman

 

[rourabpaul]

i want to know that in a main process body could we declare another process where the both process has same sensitivity list??

 

[FvM]

Review VHDL rules from a text book or a tools reference.

- You can't use a process inside a process.
- You can't use concurrent statements (e.g. a component instantiation) inside a sequential code block (a process).

When you consider the purpose of sequential code, you'll see that it won't make sense at all.

If you tell, what you want to achieve, someone can possibly point to a solution.

 

[rourabpaul]

i have function modulus,which is giving desired result individually ,but when i use it in loop in cnt,here i have
(x ³ MOD y)
i found 1 here

process(clk)
variable c: unsigned(11 downto 0):="000000000001";
variable j : integer;
variable r1: unsigned(23 downto 0);
begin
if CLK'event AND CLK = '1' then
while j=3 loop
r1:=c*x;
c:=r1(11 downto 0);
c:= modulus(c,y);
j:=j+1;
end loop;
r<=c;
end if;
end process;