problem in understanding asynchronous systems

[maheshkumar.g]

hi all, i am unable to understand the asynchronous systems u guys please help me out........as a example i am taking a asynchronous d flip flop with reset and what i don't understand is do we use clock for it if so why?. as in asynchronous the output doesnt need to depend on clock so what is the use of it?
secondly do the output depends on reset or input of the d flip flop ?
thirdly if i am not using the reset in d flip flop how would be the output..............my friends says that the output will follow the input with clock please help me...............


thanks in advance

 

[FoxyRick]

Refer to the diagram below.

A 'Clock' signal is needed to latch the data on the D input into the flip-flop.

In this case the Clock is simply allowing data into the flip-flop; think of it like an 'input enable' signal. The Clock is not synchronising the output directly.

The outputs of the flip-flop will follow changes in the D input, as long as the Clock is held high. Once the Clock falls, the data is latched.

There will be a propagation delay between data at the D input appearing at the outputs. This puts a limit on the maximum frequency of the Clock.

The Set and Clear input are asynchronous; they do not depend on the clock and will take immediate effect (after propagation delay of course). As long as a Set or Reset input is held active, the outputs of the flip-flop are forced into that state regardless of the D input or Clock.

If you do not use Set or Reset (hold them inactive) then the outputs depend only on D, as the Clock allows.

At power up, the output is indeterminate until the first Clock pulse, or Set or Reset is activated.

Is that clear?

 

[maheshkumar.g]

thank you rick if possible can u please post the waveforms also so that i can understand it more clearly also i have a doubt you said that the clock acts as a enable signal so do the input changes at positive edge of the clock or at the negative edge of the clock ..thanks in advance

 

[FoxyRick]

I don't have a timing diagram, sorry.

Think of the circuit like an SR flip-flop (on the right hand side), with an additional input circuit on the left hand side. The SR flip-flip operates normally if the additional Preset and Reset input lines are inactive.

Now, look at the left-hand side - the input circuit. The S and R of the SR flip-flop are held high (inactive) as long as the clock is low. When the clock goes high (rising edge) the D input is transferred (inverted so falling edge now, to match the NAND SR flip-flop logic) to the relevant S or R of the SR flip-flop. If the D input changes while the clock is high, the SR flip-flop sees another falling edge on the relevant S or R input and changes accordingly.

Once the clock goes low, the D input cannot propagate through the input stage and the outputs are fixed.

So, the D flip flop responds on the positive edge of the clock, or, if the clock is held high, to either edge of D.

 

[FvM]

Asynchronous D-FF is a ambiguous term, I think.

The usual terminology in literature refers to asynchronous (or level triggered) circuits as latches and synchronous (or edge triggered) circuits as flip-flops or registers.

 

[jeffrey samuel]

In general If only a part or no part of a system is controlled by the Clk pulse then it is called as asynchronous systems I am not sure of other explanations

Async systems can be made using D ff also

 

[maheshkumar.g]

thank you rick I got the concept well explained..............

thank you guys for posting your answers Jeffrey Samuel and fvm........