irisaru
Newbie level 6
Hi all,
I design 3bit idea DAC using verilogA to decode the signed binary to decimal.
My purpose is change:
100 -> 4
011 -> 3
010 -> 2
001 -> 1
000 -> 0
111 -> -1
110 -> -2
101 -> -1
I used modelwriter tools in Cadence Spectre to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wrong. I try to use logic gate with this DAC but it does not work too.
Could you please give me some advices or suggestions to solve this problem?
Thanks,
Irisaru
I design 3bit idea DAC using verilogA to decode the signed binary to decimal.
My purpose is change:
100 -> 4
011 -> 3
010 -> 2
001 -> 1
000 -> 0
111 -> -1
110 -> -2
101 -> -1
I used modelwriter tools in Cadence Spectre to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wrong. I try to use logic gate with this DAC but it does not work too.
Could you please give me some advices or suggestions to solve this problem?
Thanks,
Irisaru
