problem during initialisation

[tariavo]

n_12_hsl130e resistance

when simulated this spice circuit I have got the obscure result:
output is equal to 1.2 and 1.7.
But it seems to be 0 (open nmos transistor).
What is wrong?

info:
simulated with hsim,
spice file:
**********************************************
.lib "/home/airat/1/lib/L130E_HS12_V241.lib" TT

M1 VSS VDD out VSS N_12_HSL130E l=0.18u w=0.840u
R1 out VDD 1000000

VVDD VDD 0 1.2V
VVSS GND 0 0V

.measure DC V_OUT avg v(out)

.DC VVDD 1.2 2 0.5

.end
**********************************************

thanks!

 

[zhongdg]

Hi, what's the signal of IN and what are you want to simulate?
I don't understand why you seep the VDD and no signal at IN port?

 

[tariavo]

oh, yes : there is no signal in simulated file named "in". in fact, it is gate, and as you can see from spice file it is always VDD.

purpose of simulation is to understand..
on output should be 0 but I always watch VDD:

gate = VDD, transistor is NMOS => open transistor => V(drain) ~ v(source) ~ 0.
but it is VDD!
If resistor is excluded output is 0. But varying resistor resistance doesn't influence the result.

Added after 16 minutes:

Jesus!
I am careless!!

the problem was:
using VSS in transistor declaration:
"M1 VSS VDD out VSS N_12_HSL130E l=0.18u w=0.840u"

and using GND as ground point:
VVSS GND 0 0V

thanks everybody.
problem solved.