rybackguo
Newbie level 3
I have a design that contains redundant structures and I do not want synopsys DC to optimize my design logic away, but the tool remove the circuits by default.
How can I ask DC not to remove my logic? Also how to reduce the optimization effort? (I have very relaxed requirements for other constraints.)
Thank you!
How can I ask DC not to remove my logic? Also how to reduce the optimization effort? (I have very relaxed requirements for other constraints.)
Thank you!