Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Predefined variables in Synopsys Design Compiler

Status
Not open for further replies.

Z80

Full Member level 1
Joined
Feb 20, 2004
Messages
96
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,257
There are hundreds of them, how many do you use frequently? I'm asking because as part of my training program I was given the task of browsing though the variables and write a script containing the relevant ones, and the impression is that when I'll actually need one I won't be able to remember it, because there's zillions of them and as a beginner it's hard to tell which ones are important, and remember that there is variable x this does this and variable y that does that. So, please tell me, how many of them do you currently use?
 

Hi Z80,

The variables I ofen used no more than 30. You don't need to remember then all,

you can man then in dc_shell-t when you need the details.

wang1
 

I have counted and I have no less that 160 variables in my script. One question: can you share the script in which you set the variables you use?
 

if you use synopsys 2002/10 and after
'SYNTHESIS' is defined.
you should use
`ifndef SYNTHESIS
`endif
to replace
//synopsys translate_off
//synopsys translate_on
 

wkong_zhu, sorry, but it seems that you didn't even read my question. Please do and answer only if you have something useful to say.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top