Power aware synthesis

[geek09]

hi folks,

Iam trying my hand at power aware synthesis using synopsys upf flow. Here i will try to raise some doubts and share my experiences about this flow.

Lets start with the most basic stuff create_power_domain command...iam unclear about importance of different scopes...can't we just remain at top scope and define all our power domains from there..??

according to me, using just top scope we can do away with hierarchical definition needs in our script.

 

[geek09]

one remark: Using different scopes we can use same name nets across different power domains...
For ex: VDD_m at top scope can be accessed by VDD_m while at block level by BLOCK/VDD_m.

---------- Post added at 07:57 ---------- Previous post was at 07:54 ----------

A query about power switches:

create_power_switch switch_name
-domain domain_name
{-on_state {state_name input_supply_port {boolean_function}}}*

why do we have to mention input_supply_port in -on_state, when boolean function is a function of net connected to
control_port..??

---------- Post added at 09:01 ---------- Previous post was at 07:57 ----------

got answer for that too:

in case we have two i/p supplies in a switch, in that case we have to differentiate b/w the ON conditions of these supplies:

create_power_switch sw1 \
-domain PD_SODIUM \
-output_supply_port {vout VN3} \
-input_supply_port {vin1 VN1} \
-input_supply_port {vin2 VN2} \
-control_port {ctrl_small ON1} \
-control_port {ctrl_large ON2} \
-control_port {ss SUPPLY_SELECT} \
-on_state {partial_s1 vin1 {ctrl_small & !ctrl_large & ss}} \
-on_state {full_s1 vin1 {ctrl_small & ctrl_large & ss}} \
-on_state {partial_s2 vin2 {ctrl_small & !ctrl_large & !ss}} \
-on_state {full_s2 vin2 {ctrl_small & ctrl_large & !ss}} \
-error_state {no_small {!ctrl_small & ctrl_large}}

 

[geek09]

Level_shifters are not getting inserted in my design, there were no errors while reading the UPF, and the tool identifies the need of level shifters but cannot insert them.. I ran analyse_mv_design - level_shifters and got these messages:


Pin: add/U6/Z;
Type: Cell Output Pin; Lib Cell: ##########;


Domain: low_power;
Local Fanout: 1;
Primary Supply Nets: VDD_a, VSS_t,
Available Supply Nets: VSS_t, VDD_a,
- Driver pin related supply nets (VDD_a, VSS_t) are the primary supplies in the domain 'low_power'
this net could cause main rail violation
- Net connected to a pin with non default level shifter constraints


Can anybody help me in understanding this message..?? :/