Post-Translate simulation - ISE

[timsanr]

Hi,

I can do only Behavioral simulation. When I change simulation type to any other, UUT becomes empty and I can't add there my project.vhd file. Why it can happen? Is it because I use variables in my project?

 

[mrflibble]

Maybe you should post some more details. No idea with the current info. The only thing that springs to mind is that maybe that the files in your project have a certain association for simulation only. And then when you want a post-translate simulation it's a no go. Right click on a vhdl source file => Source properties => View association. That's the setting I mean.

Naive question: Can you synthesize your design?

When your answer is going to be "well of course it does not synthesize! this is my behavioral model!" then you have your own answer right there. No synthesis ==> no post-translate sim.

 

[timsanr]

Ehhh, I just didn't know that I need to click in Implementation=> Implement Design=> Translate/Map/P&R => Generate Synthesis Files. I thought it is generated automatically.

My design of course synthesize
Good to know/learn about association options for the future work. Thanks.