Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Post-synthesis simulation problem due to RTL clock gating

Status
Not open for further replies.

childs72

Member level 1
Member level 1
Joined
Apr 8, 2006
Messages
33
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,542
Hi guys,

I had implemented clock gating using RTL similar to below. It works well during RTL simulation. However, after synthesis, I perform simulation on post-syn netlist with sdf back-annotation. Simulation show the system does not function correctly.

Code:
assign cg__clk = clk || !clk_gate_en;
my_module my_inst ( .clk_in(cg__clk),
......);
Here is my hypothesis based on observaI understand that at post-synthesis stage, we have only ideal clock latency. However, due to the clock gate I inserted in RTL, I am seeing larger clock latency to registers inside "my_inst" (due to delay introduced by clock gate) compared to other non-clockgated registers outside of "my_inst"; this, in turns created hold time issue and the system is not able to function correctly.

Does my observation & hypothesis make sense? If yes, I believe I need to do something in order for the simulator (Cadence irun) to NOT annotate the delay at my clock gate cells. Can anyone suggest me how to do this?

Thanks!

- - - Updated - - -

Also, when I tried to report_clock_gating -gated in DC, nothing related to above RTL is reported. Does DC not recognize the code as clock gating? What should I do?
Thanks.
 

I think report_clock_gating reports clock gating that power compiler inserts, not gating you have inserted by hand.

Your gating technique is possibly a bit unreliable, anyway. I'd suggest you look in your cell library for a clock gating latch, and instantiate that.
 

Thanks jbeniston. Agreed that I should look into the cell library for clock gating latch. Meanwhile, apart from using clock gating cell, is there anything improvement that can be done on my gating technique?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top