post synthesis simulation in modelsim

[Aimerbhat]

Hello all ,

i am doing post synthesis simulation in modelsim.
I synthesized via DC with 130nm faraday library ... timing reports in DC showed no voilations of setup and hold and a slack of 228 ns for 1 Mhz .....

But in modelsim it is giving large number of setup voilations

i am confused about what went wrong ......

i also tried by reducing the clock speed to 100khz in test bench but still ....errors keep appearing....

please help


thanks in advance
regards
aimer

 

[rca]

some violations occurs in simulation after power-up or time 0ps.
the simulator has the signal going from z or u state to 1 or 0 can see an clock edge in same time of d input changing, but not real.

some violations can occur when it is an external signal (from test bench for example or analog model), that are asynchronous. If you have some synchronisation FF, the first one can have some setup & hold violations.
the solution are :
1-the timing check of this FF must be disable to avoid X propagation when a timing check in modelsim.
2-synchronize our test bench to avoid this violation.

I prefer the first solution.