dirac16
Member level 5
I'm facing a problem with a post-pnr simulation. I know the question has been asked several times out here but I have not found the answer yet.
I did post-synthesis with DC compiler, my timing constraints were met and the simulation of the netlist+SDF works as expected. I did PnR with Innovus, my timing constraints are also met, however non of Tchecks are annotated, which is possibly why I have got erroneous results. Here is a snippet of a NCverilog run:
As you see nothing of Tchecks are annotated. The design is a simple 5b counter that has got two inputs clk and reset, where reset is asynchronous to the clk signal. In my testbench I made sure that the active edge of the reset signal has enough delay from rising edge of the clk so that hopefully should not make any problem.
I did formal equivalence check with the original RTL netlist and I found the post routing netlist to be equivalent. I used -version 2.1 for my SDF file to match the standard cells, and also used -target_application verilog to optimize the sdf for simulations. So anyway what are the possible symptoms that you might think of? I am really out of any idea. Hope you shed some light.
I did post-synthesis with DC compiler, my timing constraints were met and the simulation of the netlist+SDF works as expected. I did PnR with Innovus, my timing constraints are also met, however non of Tchecks are annotated, which is possibly why I have got erroneous results. Here is a snippet of a NCverilog run:
Code:
Annotating SDF timing data:
Compiled SDF file: my.sdf.X
Log file:
Backannotation scope: Counter_tb.DUT
Configuration file:
MTM control:
Scale factors:
Scale type:
Annotation completed successfully...
SDF statistics: No. of Pathdelays = 79 Annotated = 100.00% -- No. of Tchecks = 25 Annotated = 0.00%
Building instance overlay tables: .................... Done
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 41 19
UDPs: 5 1
Primitives: 55 7
Timing outputs: 39 12
Registers: 7 4
Scalar wires: 47 -
Always blocks: 1 1
Initial blocks: 1 1
Timing checks: 35 7
Interconnect: 77 41
Simulation timescale: 1psAs you see nothing of Tchecks are annotated. The design is a simple 5b counter that has got two inputs clk and reset, where reset is asynchronous to the clk signal. In my testbench I made sure that the active edge of the reset signal has enough delay from rising edge of the clk so that hopefully should not make any problem.
I did formal equivalence check with the original RTL netlist and I found the post routing netlist to be equivalent. I used -version 2.1 for my SDF file to match the standard cells, and also used -target_application verilog to optimize the sdf for simulations. So anyway what are the possible symptoms that you might think of? I am really out of any idea. Hope you shed some light.
