eng.obd_md
Newbie level 4
Hi,
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.
In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns).
My question: is it possible to perform optimization here and how effective would that be, would I be able to simulate at 5 ns. Also, how can such optimization be performed?
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.
In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns).
My question: is it possible to perform optimization here and how effective would that be, would I be able to simulate at 5 ns. Also, how can such optimization be performed?