pastro
Junior Member level 3
Hi all,
I got an EE degree years ago, but haven't used my synchronous circuit design skills in years! I'm trying to design a circuit, but hit a conceptual snag. Hoping someone can explain if my reasoning is correct. Here's the situation below.
Suppose you have two D flip flops connected together in a two bit shift register configuration (i.e. the output of FF1 => input of FF2.) Both flip flops are clocked by the same clock source, and the input to FF1 is synchronous with this clock source.
If the propagation delay of FF1 is less than the setup + hold time of FF2, then won't the output of FF2 go metastable when the circuit is clocked, because FF2's setup and hold time requirements have been violated???
The reason I ask it that, I was thinking of making just such a shift register on a circuit I'm designing, using an a few unused flip flops on an octal Dff already on the board. However, when I checked, I found that the setup time for this Dff = 2 ns, the hold time = 2 ns, and the propagation delay = 2 ns. Therefore, setup + hold time = 4 ns > 2 ns, and we have the aforementioned possible metastability, no?
Thus, the moral of the story would be (if I'm right): you can't just assume its okay to make a shift register by hooking the inputs of one D flip flop to the outputs of another, even if the flip flops are on the same chip! You may run into metastability problems if you don't check that the propagation delay > setup + hold time.
Again, (if I'm right) wouldn't this also be a good argument for buying and using a commercial shift register, rather than making your own out of Dff's, since such metastability conditions should be designed against in the silicon of the commercial shift register unit?
I got an EE degree years ago, but haven't used my synchronous circuit design skills in years! I'm trying to design a circuit, but hit a conceptual snag. Hoping someone can explain if my reasoning is correct. Here's the situation below.
Suppose you have two D flip flops connected together in a two bit shift register configuration (i.e. the output of FF1 => input of FF2.) Both flip flops are clocked by the same clock source, and the input to FF1 is synchronous with this clock source.
If the propagation delay of FF1 is less than the setup + hold time of FF2, then won't the output of FF2 go metastable when the circuit is clocked, because FF2's setup and hold time requirements have been violated???
The reason I ask it that, I was thinking of making just such a shift register on a circuit I'm designing, using an a few unused flip flops on an octal Dff already on the board. However, when I checked, I found that the setup time for this Dff = 2 ns, the hold time = 2 ns, and the propagation delay = 2 ns. Therefore, setup + hold time = 4 ns > 2 ns, and we have the aforementioned possible metastability, no?
Thus, the moral of the story would be (if I'm right): you can't just assume its okay to make a shift register by hooking the inputs of one D flip flop to the outputs of another, even if the flip flops are on the same chip! You may run into metastability problems if you don't check that the propagation delay > setup + hold time.
Again, (if I'm right) wouldn't this also be a good argument for buying and using a commercial shift register, rather than making your own out of Dff's, since such metastability conditions should be designed against in the silicon of the commercial shift register unit?
