Pls recommend paper/book on ESD simulation strategy

[neoflash]

esd simulation

I need to learn how to simulate ESD circuit, like HBM protection, rc-trigger.

Any paper/book to reference?

Thanks,

 

[Blackuni]

simulating hbm pspice

Hi neo,

here are the list of few

1. BASIC ESD and I/O design by Sanjay
2. ESD Protection Device and Circuit Design for Advanced CMOS Technologies frm springer

Check for the class notes in this forum. file name esd_mdker.pdf

Hope it helps.

Thanks,

 

[ESDSolutions]

pspice esd simulation

I have a number of questions:

- Why do you want to simulate ESD behavior?
- Is it because there is lack of trust in the foundry supplied ESD solutions?
According to experts in the field Spice simulation of ESD is not accurate enough yet. currently models supplied by the foundry do not include high current, fast transient behavior required for such simulations.

- Is it because you are creating your own ESD solution? Be sure to watch out for patent infringement. Many companies have developed and patented ESD structures in the past. You do not want your ASIC production to be halted because it infringes on some-one's patent. Copying a protection concept from a paper of publication might bring you in to problems. Several companies spent multiple expert manyears every year looking for new solutions so it might be hard to suddenly get a new solution that is not existing (patented) yet and works from the first time.

- What simulator do you plan to use?
I guess you plan to use SPICE. As mentioned above not many models include the behavior required for ESD relevant simulations.
Some people tend to use TCAD simulators in 3D simulation. But the TCAD mesh network and process calibration influence the results drastically. Actually, even with these kind of simulations is that it is time consuming to get it right. If you can't spend full-time on the simulator it may be hard to get any relevant results!

- What is the required outcome of the simulations?
Different options:
- Proof that ESD will be fine on a full ASIC? - multiple clamps work together or not?
- Proof that ESD protection (1 clamp) is robust enough?
- Proof that ESD protection is effective (fast enough, low voltage triggering)

Depending on the answers I might provide further reference.
- Good material exists for RC-triggered BigFET simulations from the people of Freescale. As mentioned before, these solutions are patented!
- several people have spend phD's on the study of TCAD simulation for ESD. I can look up some paper references if that is what you are looking for.

Actually, this week there is an international symposium on ESD on-going in Tucson, Arizona. check-out https://www.esda.org/
I'm sure there are sessions, workshops and discussions about modeling and simulations

 

[charkyriak]

need of inductor in esd simulation

I am also trying to simulate ESD events starting with HBM....I run transient simulations
My problem is implementation of the source...
I can get the peak and the fall time but I haven't found a way to get the rise time also...
And about rc-trigger clamps...do they require an initial condition???
Thanks

 

[ESDSolutions]

inductance in esd simulations

The rise time is defined by the (parasitic) inductance and board capacitance.
If you omit the inductor, the initial current is very high (I = VHBM/1500 ohm). The inductor will prevent this sudden increase of the current and thus defines the rising edge of the current waveform

In most HBM testers this is about 5-10uH.

Most RC based MOS clamps require 0V on the capacitance as the initial condition. This directly points to problems with these type of clamps
- It is not always certain that the voltage between Vdd and Vss is zero when ESD stress is applied. There recently (2004) was a tester artifact discovered, followed by measurements that concluded that also in real HBM the capacitor might be charged up slightly before the stress
- When the IC is powered up, the RC clamp will not function anymore because the capacitance is already charged up.
- The MOS clamp is turned off after a certain period of time (defined by RC). Such time period is typically taken from the HBM standard in the order of 500ns. For stress events with longer duration the IC will be unprotected after 500ns!

Again: I don't see a need for most IC designers to make such ESD related SPICE simulations. Either you trust the foundry solution or you get out and buy/license a better solution verified by experts in the field. Don't waste valuable time in creating a new solution. The infringement risk is considerable

 

[leo_o2]

I recommend:
ESD in integrated circuit by Ali
ESD book by Albert Wang

 

[oxynitride]

Hi Neo,
May I know what exactly you want to know? Are you looking for an HBM ESD simulator netlist? There is nothing wrong in running simulations and learn from there. It is a perfectly correct way to work on ESD. We are runing a lot of ESD simulations in our university and produce world class engineers and designers who are filing many patents an year.


Since there was a reference on foundry models and its validity as well as patent infringement - more of it is presented in negative sense. Even those have many patents ensure that they circumvent others' patents. In some cases, they claim patents based on idea an unknown poor student author or an author who revealed the idea in a paper. Scaring someone on who want to learn something, using patent infringement threat is not only cheeky, but shows the arrogance.
[Some of the forum authors work for commercial companies who supposedly provide some ESD protection options (as one company put it in their website - they assume the world wide research on ESD - as if it ESD related work is owned by them and all others should use them. Be careful of those solution providers as they will file patents using your silicon and using your money].

Good luck
Oxy

 

[ESDSolutions]

I feel a bit of frustration and anger with our forum friend Oxy that I would like to understand. It is not my intention to create such feelings with anyone. On this forum, everyone shares its own experience and that's precisely what I did too.

My personal opinion is that accurate simulations are time consuming so you better have a good reason to spend the time - which you may have! Sure anyone can learn from simulations and I will not stop you. In fact I provided info and links to get you started.

Oxy, please provide reference to models from the foundry that do include NMOS snapback models for instance. I'm trying to locate such models for quite some time now without much success.

Thanks